Join us on July 7 @10:00 CEST for the third webinar of the aCCCess series dedicated to European Pilot Lines and their collaboration with Competence Centers.

In this session, discover how the FAMES Pilot Line, the euroCDP and the ASTEERICS Chips Competence Center support innovation from chip design to silicon validation and industrialisation. Through concrete feedback from Soitec and Nellow, explore how Europe’s semiconductor ecosystem helps de-risk innovation and accelerate market readiness.

📍 Programme :

10:00 – 10:05   Introduction: European Chips Act context, aCCCess project.

An Innovation Continuum: From Upstream to Downstream

Laure de Tassigny - European Projects Manager- Minalogic

10:05 – 10:12   FAMES Pilot Line: Presentation of FAMES sub-10nm technologies and Open Access

Susana Bonnetier - Open Access Chairperson - European FAMES Pilot Line – CEA

10:12 – 10:15   EuroCDP: Design resources and support services

Olivier Thomas - Deputy head of the Integrated Circuit & System division - DET IC Dash - CEA

10:15 – 10:22 - Industrial Testimonial: How FAMES helps de-risk silicon innovation? (sSOI, cybersecurity)

Sébastien Lasserre - FDSOI Product Manager - Soitec

10:22 – 10:32   ASTEERICS: Chips Competence Center mission, free training offer and ASIC support services

Philippe Flatresse - Director of Valorisation, ASTEERICS Chips Competence Center

10:32 – 10:40   Start-up Testimonial: FESO technology integration, support and fundraising journey

Jean Philippe Attané – CEO – Nellow

10:40 – 11:00   Q&A

About aCCCess webinar series on Technology offers

Each session spotlights one pilot line and one competence centre and also focus on collaborations between ENCCC actors and user experiences.

These sessions will help our communities to understand:

• What are pilot lines and how can their services be accessed?

• What technological resources in microelectronics exist in European ecosystems and how can they be leveraged?

• Do European Competence Centres offer services complementary to each other?